D Flip- Flop pada VHDL

Sebuah contoh program vhdl dari D flip-flop edge triggered positif dengan asynchronous Reset:

library ieee;
use ieee.std_logic_1164.all;
entity DFF_RST is
port (CLK, RESET, D : in std_logic;
Q : out std_logic);
end DFF_RST;

architecture BEHAV_DFF of DFF_RST is
begin
DFF_PROCESS: process (CLK, RESET)
begin
if (RESET = ‘1’) then
Q <= ‘0’;
elsif (CLK’event and CLK = ‘1’) then
Q <= D;
end if;
end process;
end BEHAV_DFF;

Library dan Package VHDL

Library IEEE:

use IEEE.std_logic_1164.all;

use IEEE.std_logic_textio.all;

use IEEE.std_logic_arith.all;

use IEEE.numeric_bit.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_signed.all;

use IEEE.std_logic_unsigned.all;

use IEEE.math_real.all;

use IEEE.math_complex.all;


Library STD:

use STD.standard.all;

use STD.textio.all;

Library WORK:
pendeklarasian yang implisit,dimana semua source codenya akan dimasukkan ke library tersebut.



example:

use WORK.data_types.all;